Goal is to be just close enough to RISC-V to get benefit of work on it, but leave behind the design errors, so formal verification and compiler targeting can be ported with minimal effort. Credible lists of RISC-V design errors have been published.
Goal is to be just close enough to RISC-V to get benefit of work on it, but leave behind the design errors, so formal verification and compiler targeting can be ported with minimal effort. Credible lists of RISC-V design errors have been published.