> "...some form of parallelism (so that pipelines can be created with machine code and not just heuristics)..."
Not sure exactly what is meant by this. Either the answer is the hardware already automatically maximizes parallelization (https://en.wikipedia.org/wiki/Superscalar_processor) or the answer is that there's no way to physically rewire a chip on the fly.
> "...since it is probably easier and better to branch predict in software than in hardware..."
Been tried, doesn't seem to have been that successful IIRC. A cursory Google shows that x86 had (and dropped) branch hint prefixes for instructions and the Cell's SPUs had branch hint instructions as well. Various languages also allow exposing branch prediction hints to the compiler, e.g.: https://en.cppreference.com/w/cpp/language/attributes/likely
Things like that already exist, e.g. for x86: https://c9x.me/x86/html/file_module_x86_id_252.html
> "...some form of parallelism (so that pipelines can be created with machine code and not just heuristics)..."
Not sure exactly what is meant by this. Either the answer is the hardware already automatically maximizes parallelization (https://en.wikipedia.org/wiki/Superscalar_processor) or the answer is that there's no way to physically rewire a chip on the fly.
> "...since it is probably easier and better to branch predict in software than in hardware..."
Been tried, doesn't seem to have been that successful IIRC. A cursory Google shows that x86 had (and dropped) branch hint prefixes for instructions and the Cell's SPUs had branch hint instructions as well. Various languages also allow exposing branch prediction hints to the compiler, e.g.: https://en.cppreference.com/w/cpp/language/attributes/likely