The biggest limiting factor is the ability to etch deep holes with a high aspect ratio. Shrinking individual memory cells along any axis is of limited use (fewer electrons means less durability), so you can't make layers much thinner. Making holes wider can get you more layers, but isn't really a net win for total density. So far, nobody has started stacking more than two decks of layers, so I don't know if we have good data on how cost and yield scale when going all-out on string stacking to reach extreme layer counts. As an alternative, there's R&D into using wider holes, and then splitting the vertical channels in half, giving you two semicircular memory cells per layer rather than one circular cell.
There's also a need to keep shrinking the peripheral circuitry as the number of memory cells stacked above each mm^2 of buffers and charge pumps keeps growing.
I've been reporting on it for the past 5 years, including a recent interview with one of Micron's lead engineers about their 176L NAND, which I haven't written up and published yet. https://www.anandtech.com/Author/182
Technically part-time, paid as a freelancer. Only two or three of the senior editors are on salary. It's not a lucrative line of work, but most of the time it's pretty fun.
Oh wow. The quality is absolutely amazing though. Thank You. While there are less content to write purely just on DRAM, NAND and storage, some of those reporting still takes a long time to investigate and write. Never thought it was freelance.
There's also a need to keep shrinking the peripheral circuitry as the number of memory cells stacked above each mm^2 of buffers and charge pumps keeps growing.