RISC is the secret sauce that allows M2 to decode four instructions per clock cycle, due to the constant instruction length, and that is what gives the M2 a speed advantage over CISC instruction sets. The snapdragon CPUs aren't trying to decode four instructions per clock cycle, so they aren't taking advantage of that feature of RISC instructions.
Got it. It is not enough to have a fixed width instruction set, you also have to actually decode and execute them faster after decoding. Wonder at what point we will start seeing competitive ARM CPUs.
