As a C programmer, I don't think C is suitable for such a fundamentally parallel architecture as an FPGA. I would prefer a higher level language, maybe declarative, where it is up to the compiler to lay out the parallel operations. Unfortunately the engineering culture gap from HDL to a high level language is much wider than to C.
Actually it's easier and more natural to translate a (domain-specific) high level language into RTL than trying to fit an alien but so-called "general-purpose" C.
I'm using a language which translates into Verilog, but features native support for expressing things like FSMs, pipelines, buses, FIFOs - and something as simple as this makes HDL coding much simpler and much less error-prone than a conventional low-level RTL.
This is because C, as I understand it, is a language that best described the fundamental workings of processors, and let you work with a thin-abstraction layer over the cpu/memory architecture.
FPGA don't have this traditional cpu/memory architecture, and as a result, C fits them poorly.
Exactly. C assumes too much about the hardware semantics, it's got a peculiar memory model, sequential execution and all that. There are tricks, of course, allowing to get out of the C box a little bit - e.g., using multiple address spaces to simulate distinct memory and memory-like blocks, but it's still unnatural and do not make hardware description any simpler than doing it manually in RTL level.
