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> I want to make some difference. But I'm not sure where to start...

1. Take a promising language, improve it where necessary.

2. Add excellent support for translation to VHDL and Verilog. The generated HDL code has to be readable, editable, and it has to reflect the structure of the original code more or less 1:1. You also need to support "inline VHDL/Verilog" (like inline assembly in software). Otherwise, your language doesn't integrate into the ecosystem of synthesis software, simulators, vendor-dependent Map/P&R, and existing IP cores, which makes it useless in the real world. This is the main reason why all innovative VHDL/Verilog replacements have failed so far. Without this feature, there's just no way your language is going to gain any significant market share.



Are you referring to a new DSL based on software languages, something like MyHDL? I think this is definitely promising for designs that are started from scratch. However, as soon as there is need to integrate with other legacy code, it falls back to the current painful way of manual integration.

What do you think about an IDE that supplements existing HDL languages? Not as drastic as making a shiny new language, but it avoids many challenges you brought up.

Since you are coming from a CS background, do you have recommendation for good IDE frameworks that can be leveraged?


2. I am curious to hear what you think about our solution of wrapping existing VHDL/Verilog in an external task in Cx? http://cx-lang.org/documentation/tasks#external


Very nicely done!

Is there a way to get in contact with you? I suppose you're either Nicolas or Matthieu?


Yep, I'm Matthieu! You can send me an email at matthieu.wipliez at synflow.com




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